In the first industrial processes for burn-in of integrated circuits, these were arranged at elevated temperatures and were provided with the necessary supply voltages, and the components were tested separately after a specified period of time under these circumstances in a testing device designed for this purpose; after sorting of the faulty circuits, the remaining circuits were again subjected to operation at elevated temperatures, and these components were again tested after a specified period of time, with repetition of this process until the desired low error rate was reached in the testing. This type of testing, however, is vitiated by considerable drawbacks, because the circuits are to be handled repeatedly, and even though the process can take place automatically, a not insignificant part of the circuits has to be rejected because of purely mechanical damage.
The U.S. Pat. No. 4,379,259 discloses a process for functional testing and burn-in of storage circuits, which is vitiated by the drawback that the circuits form part of functional units and can therefore only be tested in large or small groups, and an error in one of the circuits in a group makes it impossible to proceed with the testing for the other circuits in the group.
The U.S. Pat. No. 4,507,544 and 4,374,317 disclose devices for testing integrated circuits at elevated temperatures, but the devices described there are vitiated by considerable drawbacks since it is only possible to transfer a limited number of signals between the circuits under testing and the surroundings.